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Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling.
Akira Tsuchiya
Masanori Hashimoto
Hidetoshi Onodera
Published in:
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2005)
Keyphrases
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high speed
low power
input output
real time
low cost
neural network
social networks
frame rate
low latency
power dissipation
cmos technology
information systems
evolutionary algorithm
query optimization
power consumption
lower cost