A 4-kb Low-Power SRAM Design With Negative Word-Line Scheme.
Chua-Chin WangChing-Li LeeWun-Ji LinPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2007)
Keyphrases
- low power
- power consumption
- single chip
- low cost
- low power consumption
- high speed
- logic circuits
- vlsi architecture
- power reduction
- mixed signal
- digital signal processing
- cmos technology
- gate array
- high power
- power dissipation
- knowledge base
- wireless transmission
- vlsi circuits
- power saving
- power management
- image sensor
- delay insensitive
- signal processor
- nm technology
- analog to digital converter
- real time