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Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology.

Farshad MoradiGeorgios PanagopoulosGeorgios KarakonstantisHooman FarkhaniDag T. WislandJens Kargaard MadsenHamid MahmoodiKaushik Roy
Published in: Microelectron. J. (2014)
Keyphrases
  • cmos technology
  • power consumption
  • low power
  • nano scale
  • low voltage
  • single chip
  • power dissipation
  • case study
  • spl times
  • optical flow
  • high resolution
  • high speed
  • design process