Noise Effects on Performance of Low Power Design Schemes in Deep Submicron Regime.
Mohamed AbbasMakoto IkedaKunihiro AsadaPublished in: DFT (2004)
Keyphrases
- low power
- single chip
- low cost
- high speed
- power consumption
- low power consumption
- mixed signal
- vlsi circuits
- vlsi architecture
- logic circuits
- digital signal processing
- gate array
- power dissipation
- cmos technology
- design process
- high power
- energy dissipation
- ultra low power
- design methodology
- nm technology
- noise level
- power saving
- vlsi implementation
- wireless transmission
- image sensor
- low complexity