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A One-Chip Scalable 8 * 8 ATM Switch LSI Employing Shared Buffer Architecture.
Yasuro Shobatake
Masahiko Motoyama
Emiko Shobatake
Takashi Kamitake
Shoichi Shimizu
Makoto Noda
Kenji Sakaue
Published in:
IEEE J. Sel. Areas Commun. (1991)
Keyphrases
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high speed
vlsi implementation
memory access
analog vlsi
latent semantic indexing
management system
multithreading
packet switching
low cost
atm networks
design considerations
scalable distributed
software architecture
functional verification
hardware implementation
cmos technology
low power
mixed signal
random access memory