A One-Chip Scalable 8 * 8 ATM Switch LSI Employing Shared Buffer Architecture.
Yasuro ShobatakeMasahiko MotoyamaEmiko ShobatakeTakashi KamitakeShoichi ShimizuMakoto NodaKenji SakauePublished in: IEEE J. Sel. Areas Commun. (1991)
Keyphrases
- high speed
- vlsi implementation
- memory access
- analog vlsi
- latent semantic indexing
- management system
- multithreading
- packet switching
- low cost
- atm networks
- design considerations
- scalable distributed
- software architecture
- functional verification
- hardware implementation
- cmos technology
- low power
- mixed signal
- random access memory