ME64 - A Highly Scalable Hardware Parallel Architecture Motion Estimation in FPGA.
Diogo ZandonaiSergio BampiMarcel BergermanPublished in: SBCCI (2003)
Keyphrases
- parallel architecture
- highly scalable
- motion estimation
- hardware implementation
- systolic array
- parallel processing
- field programmable gate array
- shared memory
- variable block size motion estimation
- motion compensation
- motion vectors
- hardware architecture
- optical flow
- video coding
- inter frame
- video compression
- high level synthesis
- image sequences
- parallel implementation
- signal processing
- video sequences
- distributed memory
- dedicated hardware
- computational complexity
- computer vision
- synthetic aperture sonar
- reference frame
- super resolution
- block matching
- efficient implementation
- hardware design
- processing elements
- motion estimator
- image processing
- xilinx virtex
- coding efficiency
- massively parallel
- image processing algorithms