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A single-event upset robust, 2.2 GHz to 3.2 GHz, 345 fs jitter PLL with triple-modular redundant phase detector in 65 nm CMOS.
Jeffrey Prinzie
Michiel Steyaert
Paul Leroux
Jorgen Christiansen
Paulo Moreira
Published in:
A-SSCC (2016)
Keyphrases
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high speed
power consumption
feature selection
low cost
frequency band
dual band
low power
circuit design
real time
delay insensitive
intel xeon