Design flow of robust routed power distribution for low power ASIC.
Dae Woon KangYong-Bin KimPublished in: ISCAS (1) (2002)
Keyphrases
- low power
- single chip
- low cost
- power consumption
- low power consumption
- high speed
- vlsi architecture
- power distribution
- logic circuits
- digital signal processing
- cmos technology
- power dissipation
- gate array
- design methodology
- high power
- power reduction
- circuit design
- image processing
- neural network
- mixed signal
- wireless transmission
- real time
- markov chain