Estimating worst-case latency of on-chip interconnects with formal simulation.

Freek Verbeek Nike van Vugt

Published in: FMCAD (2017)

Keyphrases

worst case
np hard
upper bound
input output
lower bound
low cost
average case
simulation model
single chip
simulation models
high speed
greedy algorithm
approximation algorithms
formal model
high density
response time
vlsi implementation
real time
simulation environment
mathematical model
programmable logic
analog vlsi