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Inversion/non-inversion reconfiguration scheme for a 0.18 J.1m CMOS process optically reconfigurable gate array VLSI.
Takahiro Watanabe
Minoru Watanabe
Published in:
MWSCAS (2012)
Keyphrases
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gate array
low power
low cost
image reconstruction
logic circuits
high speed
multistage
neural network
image processing
general purpose
image compression
power consumption
hardware implementation
vlsi circuits
reconfigurable architecture