A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design.
Shyh-Jye JouChang-Yu ChenEn-Chung YangChau-Chin SuPublished in: IEEE J. Solid State Circuits (1997)
Keyphrases
- low power
- high speed
- logic circuits
- power dissipation
- single chip
- power consumption
- low power consumption
- vlsi architecture
- low cost
- digital signal processing
- cmos technology
- wireless transmission
- gate array
- power reduction
- mixed signal
- vlsi circuits
- ultra low power
- high power
- hough transform
- nm technology
- design process
- power saving
- image sensor
- delay insensitive
- data flow
- image processing