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An Architecture for High-Performance Scalable Shared-Memory Multiprocessors Exploiting On-Chip Integration.
Manuel E. Acacio
José González
José M. García
José Duato
Published in:
IEEE Trans. Parallel Distributed Syst. (2004)
Keyphrases
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shared memory multiprocessors
high speed
highly scalable
data intensive
data integration
three dimensional
memory efficient
image sequences
image processing
signal processing
high efficiency
data model
coarse grained
bayesian networks
low latency
evolvable hardware
signal processor