12-bit non-calibrating noise-immune redundant SAR ADC for system-on-a-chip.
A. ShrivastavaPublished in: ISCAS (2006)
Keyphrases
- analog to digital converter
- random access memory
- synthetic aperture radar
- low cost
- single chip
- noise level
- sar images
- noise reduction
- signal subspace
- speckle noise
- high speed
- noisy data
- signal to noise ratio
- multiplicative noise
- missing data
- low power
- parameter estimation
- high density
- received signal
- multiscale
- image reconstruction
- analog vlsi
- automatic target recognition
- anomaly detection
- additive noise
- image processing