Single chip DSP array processor: 100 Million + transistors with multithreading approach.

Radovan Sernec Matej Zajc Jurij F. Tasic

Published in: EUSIPCO (1998)

Keyphrases

single chip
array processor
multithreading
low power
high speed
power consumption

low cost
semantic network
highly efficient
parallel computing
scan line
computational power

signal processing
coarse grained
memory efficient
data partitioning
distributed memory
image sensor

shared memory
message passing
fine grained
real time
pairwise
image processing