An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network.
Anju P. JohnsonDavid M. HallidayAlan G. MillardAndy M. TyrrellJon TimmisJunxiu LiuJim HarkinLiam McDaidShvan KarimPublished in: SSCI (2016)
Keyphrases
- fault tolerant
- fault tolerance
- distributed systems
- interconnection networks
- low cost
- peer to peer
- hardware implementation
- load balancing
- network structure
- neural network
- high availability
- hardware architecture
- safety critical
- computer systems
- state machine
- hardware architectures
- evolvable hardware
- communication networks
- input patterns
- application specific
- multimedia