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Minimizing clock latency range in robust clock tree synthesis.
Wen-Hao Liu
Yih-Lang Li
Hui-Chi Chen
Published in:
ASP-DAC (2010)
Keyphrases
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high speed
power consumption
wide range
parameter tuning
data sets
data structure
computationally efficient
low latency
duty cycle
real time
databases
case study
response time
robust estimation