A high-speed, low-power 3D-SRAM architecture.

H. Henry Nho Mark Horowitz S. Simon Wong

Published in: CICC (2008)

Keyphrases

low power
high speed
vlsi architecture
power consumption
cmos technology
low cost
single chip
real time
high power
nm technology
mixed signal
wireless transmission
power management
logic circuits
low power consumption
power reduction
digital signal processing
signal processing
gate array