Improving STT MRAM storage density through smaller-than-worst-case transistor sizing.

Wei Xu Yiran Chen Xiaobin Wang Tong Zhang

Published in: DAC (2009)

Keyphrases

worst case
design considerations
upper bound
high speed
lower bound
average case
error bounds
data storage
data sets
data structure
computational complexity
approximation algorithms
integrated circuit
storage and retrieval
random access memory
storage devices
neural network