Reliable memory PUF design for low-power applications.

Mohammad Saber Golanbari Saman Kiamehr Rajendra Bishnoi Mehdi Baradaran Tahoori

Published in: ISQED (2018)

Keyphrases

low power
single chip
power consumption
power dissipation
low cost
high speed
low power consumption
vlsi architecture
logic circuits
gate array
digital signal processing
high power
mixed signal
cmos technology
design process
power reduction
wireless transmission
nm technology
real time