3.6 A 10Gb/s hybrid ADC-based receiver with embedded 3-tap analog FFE and dynamically-enabled digital equalization in 65nm CMOS.
Ayman ShafikEhsan Zhian TabasyShengchang CaiKeytaek LeeSebastian HoyosSamuel PalermoPublished in: ISSCC (2015)
Keyphrases
- analog to digital converter
- delta sigma
- mixed signal
- cmos technology
- circuit design
- cmos image sensor
- low power
- sigma delta
- image sensor
- high speed
- single chip
- multi channel
- wide dynamic range
- embedded systems
- decision feedback
- analog vlsi
- dynamic range
- channel estimation
- metal oxide semiconductor
- focal plane
- multipath
- parallel processing
- power consumption
- infrared
- low voltage
- image processing
- watermarking algorithm
- nm technology
- dynamic random access memory
- low cost