Runtime reconfigurable DSP unit using one's complement and Minimum Signed Digit.
Travis MandersonLaurence TurnerPublished in: FPL (2012)
Keyphrases
- systolic array
- digital signal
- signal processing
- reconfigurable architecture
- low cost
- digital signal processing
- high speed
- data flow
- digital signal processor
- functional units
- hardware implementation
- general purpose
- field programmable gate array
- square error
- multi objective evolutionary
- databases
- database
- processing units
- error rate
- computer vision
- genetic algorithm
- neural network