A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing.

Florian Zaruba Fabian Schuiki Luca Benini

Published in: Hot Chips Symposium (2020)

Keyphrases

floating point
instruction set
sparse matrices
floating point arithmetic
fixed point
square root
high speed
real time
computer architecture
hardware architecture
low cost
parallel processing