A 4.75GOPS single-chip programmable processor array consisting of a multithreaded processor and multiple SIMD and IO processors.
Young-Don BaeIn-Cheol ParkPublished in: CICC (2004)
Keyphrases
- processor array
- single chip
- embedded processors
- parallel implementation
- highly parallel
- parallel algorithm
- low power
- mesh connected
- low cost
- signal processor
- parallel computers
- distributed memory
- image sensor
- parallel processing
- power consumption
- array processor
- high speed
- parallel programming
- massively parallel
- binary images
- data management