A Low-Power 2-Dimensional Bypassing Multiplier Using 0.35 um CMOS Technology.

Chua-Chin Wang Gang-Neng Sung

Published in: ISVLSI (2006)

Keyphrases

cmos technology
low power
power consumption
low cost
high speed
low voltage
single chip
digital signal processing
power dissipation
low power consumption
mixed signal
floating point
image sensor
computer vision
parallel processing
hardware and software