Time interleaved C-2C SAR ADC with background timing skew calibration in 65nm CMOS.
Luke WangQiwei WangAnthony Chan CarusonePublished in: ESSCIRC (2014)
Keyphrases
- cmos technology
- analog to digital converter
- camera calibration
- high speed
- synthetic aperture radar
- silicon on insulator
- foreground objects
- low power
- circuit design
- aspect ratio
- nm technology
- low cost
- sar images
- single chip
- automatic target recognition
- sar imagery
- parameter estimation
- camera parameters
- power consumption
- image processing
- image reconstruction
- analog vlsi