A Low-Power Deconvolutional Accelerator for Convolutional Neural Network Based Segmentation on FPGA: Abstract Only.
Shuanglong LiuXinyu NiuWayne LukPublished in: FPGA (2018)
Keyphrases
- low power
- high speed
- low cost
- low power consumption
- single chip
- power consumption
- gate array
- power reduction
- digital signal processing
- field programmable gate array
- neural network
- wireless transmission
- high power
- hardware implementation
- level set
- real time
- cmos technology
- vlsi architecture
- vlsi circuits
- multiscale
- delay insensitive
- image segmentation
- parallel implementation
- image sensor
- signal processing
- logic circuits
- general purpose
- nm technology