Digital Leakage Compensation for a Low-Power and Low-Jitter 0.5-to-5GHz PLL in 10nm FinFET CMOS Technology.
Yongping FanBo XiangDan ZhangJames S. AyersKuan-Yueh James ShenAndrey MezhibaPublished in: ISSCC (2019)
Keyphrases
- cmos technology
- low power
- mixed signal
- high speed
- power consumption
- low power consumption
- low cost
- low voltage
- clock frequency
- cmos image sensor
- single chip
- digital signal processing
- power dissipation
- image sensor
- packet loss
- silicon on insulator
- parallel processing
- power management
- image processing
- hardware and software
- nm technology