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A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points.
Arijit Raychowdhury
Swaroop Ghosh
Swarup Bhunia
Debjyoti Ghosh
Kaushik Roy
Published in:
ETS (2005)
Keyphrases
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vlsi implementation
low overhead
data streams
load balancing
design methodology
real time
data sets
pairwise
fault diagnosis
parallel algorithm
power consumption