Cost-efficient FPGA layered LDPC decoder with serial AP-LLR processing.
Oana BoncaloAlexandru AmaricaiAndrei HeraValentin SavinPublished in: FPL (2014)
Keyphrases
- cost efficient
- turbo codes
- fpga implementation
- real time
- ldpc codes
- channel coding
- distributed video coding
- low density parity check
- error correction
- real time image processing
- parallel architecture
- low complexity
- high speed
- decoding algorithm
- low cost
- governmental organizations
- message passing
- transform domain
- error resilient
- image quality
- hardware implementation
- signal processing
- field programmable gate array
- reconfigurable hardware
- video compression