Login / Signup
7.7 A 2.16pJ/b 112Gb/s PAM-4 Transceiver with Time-Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28nm CMOS.
Yen-Po Lin
Pen-Jui Peng
Chun-Chang Lu
Po-Ting Shen
Yun-Cheng Jao
Ping-Hsuan Hsieh
Published in:
ISSCC (2024)
Keyphrases
</>
high speed
ultra low power
low power
cmos technology
silicon on insulator
power consumption
nm technology
low rate
electronic commerce
low cost
circuit design
power supply
frequency response
metal oxide semiconductor
delay insensitive
analog vlsi