RiCaSi: Rigorous Cache Side Channel Mitigation via Selective Circuit Compilation.
Heiko MantelLukas ScheidelThomas SchneiderAlexandra WeberChristian WeinertTim WeißmantelPublished in: CANS (2020)
Keyphrases
- countermeasures
- high speed
- data access
- analog vlsi
- electronic circuits
- circuit design
- prefetching
- hit rate
- silicon on insulator
- memory hierarchy
- risk management
- cmos technology
- back end
- query processing
- mathematical foundations
- digital circuits
- low cost
- power analysis
- cache management
- logic circuits
- database
- cache replacement
- semantic caching
- website
- web caching
- smart card
- main memory
- knowledge compilation
- access patterns