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A CMOS Low-Voltage Super Follower Using Quasi-Floating Gate Techniques.
Juan Jesús Ocampo Hidalgo
J. Alducín-Castillo
I. Vázquez-Álvarez
Luz Noé Oliva-Moreno
Jesus E. Molinar-Solis
Published in:
J. Circuits Syst. Comput. (2018)
Keyphrases
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low voltage
floating gate
power line
design considerations
cmos technology
random access memory
power management
neural network
circuit design
power consumption
mixed signal
battery powered
synaptic weights
leakage current