Scalable and low power LDPC decoder design using high level algorithmic synthesis.

Yang Sun Joseph R. Cavallaro Tai Ly

Published in: SoCC (2009)

Keyphrases

low power
single chip
low density parity check
power consumption
low cost
vlsi architecture
low power consumption
logic circuits
high speed
digital signal processing
gate array
power reduction
low complexity
mixed signal
distributed video coding
ldpc codes
ultra low power
application specific
vlsi circuits