High-performance CMOS variability in the 65-nm regime and beyond.
Kerry BernsteinDavid J. FrankAnne E. GattikerWilfried HaenschBrian L. JiSani R. NassifEdward J. NowakDale J. PearsonNorman J. RohrerPublished in: IBM J. Res. Dev. (2006)
Keyphrases
- cmos technology
- silicon on insulator
- embedded dram
- nm technology
- metal oxide semiconductor
- low cost
- high speed
- random access memory
- low power
- power consumption
- analog vlsi
- cost effective
- power supply
- scientific computing
- parallel processing
- low voltage
- neural network
- cmos image sensor
- intra class
- high efficiency
- genetic algorithm