Optimized Arithmetic Hardware Design based on Hierarchical Formal Verification.
Nikhil KikkeriPeter-Michael SeidelPublished in: ICECS (2006)
Keyphrases
- formal verification
- hardware design
- model checking
- hardware implementation
- automated verification
- model checker
- fpga hardware
- symbolic model checking
- bounded model checking
- program slicing
- low cost
- field programmable gate array
- hardware software
- machine learning
- parallel processing
- fine grained
- general purpose
- knowledge representation
- image processing