A survey on decoding schedules of LDPC convolutional codes and associated hardware architectures.
Hayfa Ben ThameurBertrand Le GalNadia KhoujaFethi TliliChristophe JégoPublished in: ISCC (2017)
Keyphrases
- convolutional codes
- channel coding
- hardware architectures
- low density parity check
- error correction
- ldpc codes
- computational power
- variable length
- error propagation
- source coding
- hardware architecture
- turbo codes
- video transmission
- unequal error protection
- additive white gaussian noise
- error resilience
- error resilient
- image transmission
- bit error rate
- wireless channels
- image processing
- design procedure
- error control
- coded images
- viterbi algorithm
- fading channels
- compressed video
- computer simulation
- low cost