An Asynchronous AER Circuits with Rotation Priority Tree Arbiter for Neuromorphic Hardware with Analog Neuron.
Jinsong WeiJilin ZhangXumeng ZhangZuheng WuChunmeng DouTuo ShiHong ChenQi LiuPublished in: ASICON (2019)
Keyphrases
- floating gate
- address event representation
- synaptic weights
- circuit design
- neural network
- bio inspired
- digital circuits
- communication protocol
- fully functional
- tree structure
- rotation invariant
- analog vlsi
- analog circuits
- delay insensitive
- artificial neural networks
- biologically plausible
- data structure
- image processing