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A 4MHz BW 69dB SNDR continuous-time delta-sigma modulator with reduced sensitivity to clock jitter.

Yu-Cheng ChangWei-Hao ChiuChen-Chien LinTsung-Hsien Lin
Published in: A-SSCC (2011)
Keyphrases
  • delta sigma
  • high speed
  • noise shaping
  • analog to digital converter
  • image coding
  • power consumption
  • error diffusion
  • packet loss
  • fpga device
  • real time
  • delta sigma modulators