Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism.
Saket SrivastavaAissa MeloukiBashir M. Al-HashimiPublished in: NANOARCH (2009)
Keyphrases
- selection mechanism
- analog vlsi
- high speed
- management system
- low cost
- software architecture
- cmos image sensor
- real time
- circuit design
- design considerations
- polynomial neural networks
- cmos technology
- defect detection
- communication protocol
- network architecture
- power consumption
- metadata
- power supply
- social tagging
- hybrid learning
- low power