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Charge Scavenging Gate Coupled Hierarchical Bitline Scheme for Ultra-Low Power SRAMs in 65nm LSTP CMOS.
Mukesh Kumar Srivastav
Rimjhim
Govind Soni
Umang Mittal
Rupali Tewari
Riya Yadav
Anuj Grover
Kedar Janardan Dhori
Harsh Rawat
Published in:
ICECS (2021)
Keyphrases
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ultra low power
cmos technology
low power
nm technology
low cost
power consumption
metal oxide semiconductor
high speed
low voltage
digital signal processing
silicon on insulator
single chip
bi directional
neural network
power dissipation
real time
vlsi circuits
multiresolution
metal oxide
multiscale