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An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz.
José A. Tierno
Sergey V. Rylov
Alexander V. Rylyakov
Montek Singh
Steven M. Nowick
Published in:
ASYNC (2002)
Keyphrases
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fir filters
vlsi implementation
asynchronous communication
circuit design
finite impulse response
frequency response
filter design
impulse response
computer vision
filter bank
lifting scheme
pattern recognition
standard deviation
digital filters