Login / Signup
A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing.
Kazutoshi Kobayashi
Masao Aramoto
Yoichi Yuyama
Akihiko Higuchi
Hidetoshi Onodera
Published in:
ASP-DAC (2005)
Keyphrases
</>
level parallelism
high speed
single chip
instruction set
vlsi implementation
management system
memory access
multithreading
low cost
resource allocation
high density
parallel execution
memory bandwidth
computation intensive
memory subsystem