Influence of passive hardware redundancy on differential power analysis resistance of AES cipher implemented in FPGA.
Vojtech MiskovskýHana KubátováMartin NovotnýPublished in: Microprocess. Microsystems (2017)
Keyphrases
- advanced encryption standard
- differential power analysis
- s box
- hardware implementation
- field programmable gate array
- fpga device
- block cipher
- reconfigurable hardware
- low cost
- fpga hardware
- hardware architecture
- parallel hardware
- real time
- software implementation
- hardware design
- power analysis
- fpga implementation
- encryption algorithms
- fpga technology
- single chip
- pipelined architecture
- encryption algorithm
- hardware software
- data acquisition
- initial conditions
- massively parallel
- high speed
- hardware and software
- efficient implementation
- lightweight
- countermeasures
- embedded systems