Pre-bond testable low-power clock tree design for 3D stacked ICs.
Xin ZhaoDean L. LewisHsien-Hsin S. LeeSung Kyu LimPublished in: ICCAD (2009)
Keyphrases
- low power
- power consumption
- high speed
- single chip
- low power consumption
- low cost
- vlsi architecture
- logic circuits
- gate array
- cmos technology
- power dissipation
- power reduction
- digital signal processing
- vlsi circuits
- ultra low power
- high power
- mixed signal
- design process
- nm technology
- power saving
- efficient implementation
- signal processor