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A design of source-degenerated CMOS active negative group delay circuit using bonding wire.
Girdhari Chaudhary
Junhyung Jeong
Qi Wang
Yongchae Jeong
Published in:
IEICE Electron. Express (2019)
Keyphrases
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circuit design
power dissipation
high speed
power consumption
neural network
cmos technology
positive and negative
engineering design
digital circuits
parallel processing
design considerations
electronic circuits
delay insensitive
vlsi circuits
chip design
phase locked loop