Login / Signup

A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability.

Patrik Larsson
Published in: IEEE J. Solid State Circuits (1999)
Keyphrases
  • high speed
  • power consumption
  • low power
  • cmos technology
  • nm technology
  • low cost
  • high frequency
  • real time
  • neural network
  • high levels
  • error detection
  • circuit design
  • image recovery
  • vlsi circuits
  • fpga device