Parallel Architecture of Reconfigurable Hardware for Massive Output Active Noise Control.
Diego MendezDavid ArevaloDiego PatiñoEduardo A. GerleinRicardo QuintanaPublished in: Parallel Process. Lett. (2019)
Keyphrases
- parallel architecture
- hardware implementation
- reconfigurable hardware
- processing elements
- parallel processing
- shared memory
- high level synthesis
- distributed memory
- low cost
- parallel implementation
- field programmable gate array
- fine grain
- efficient implementation
- real time
- hardware architecture
- signal processing
- hardware design
- functional units
- image processing algorithms
- parallel algorithm
- evolvable hardware
- image segmentation