A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage.

Hafijur Rahman Chaitali Chakrabarti

Published in: ISCAS (2) (2004)

Keyphrases

logic circuits
low power
power consumption
cmos technology
high speed
leakage current
computer vision
low cost
real time
case study
power dissipation
nm technology
query language