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Reliable computing with ultra-reduced instruction set co-processors.
Aravindkumar Rajendiran
Sundaram Ananthanarayanan
Hiren D. Patel
Mahesh V. Tripunitara
Siddharth Garg
Published in:
DAC (2012)
Keyphrases
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instruction set
floating point
computer architecture
application specific
embedded systems
level parallelism
memory subsystem
instruction set architecture
real time
artificial intelligence
computer science
data model
ibm power processor