Clock power reduction for virtex-5 FPGAs.
Qiang WangSubodh GuptaJason Helge AndersonPublished in: FPGA (2009)
Keyphrases
- power reduction
- power consumption
- field programmable gate array
- fpga device
- hardware implementation
- reconfigurable hardware
- low power
- clock gating
- power saving
- low cost
- embedded systems
- parallel computing
- energy efficiency
- hardware software
- image processing algorithms
- digital signal processing
- high speed
- computing systems
- efficient implementation
- multithreading
- data center
- signal processing
- power dissipation
- image processing
- massively parallel
- energy saving
- computer vision
- hardware and software